An exciting opportunity has arisen for a talented Senior Mixed-Signal Verification Engineer. You will participate in all aspects of verification for complete mixed signal IC developments, work on complex verification systems and contribute towards improvements in verification methodology within Cirrus Logic. This is a real chance for you to get heavily involved in cutting edge projects working in a global organisation. In return, we offer you a great range of benefits including personal and professional development, a uniquely flat culture and much, much more!
- Leadership of mixed signal verification activities, including resource planning, task assignment and reporting through to the delivery of thoroughly verified ICs.
- Definition of IC verification strategy for complex mixed signal systems. Including modelling and selection of appropriate simulation techniques and environments.
- Definition of IC verification plans linking product requirements through to detailed testcases.
- Development of reliable and reusable mixed signal testbenches, compliant with industry standard verification techniques, for complex subsystems and mixed signal ICs.
- Participate in verification Expert Groups to identify and drive enhancements to the verification process.
- Tool and methodology support for other Engineers working on mixed signal verification activities.
- Hands-on project verification involvement, including testbench development, modelling of analog systems, netlisting, and simulation.
- Mentorship and support of other Engineers to develop their skills and improve the verification practices within the team.
- Collaboration with other Engineering disciplines to maximize efficiency of development activities.
Required Skills and Qualifications
- Degree or equivalent in Electronics/Computer Science or other related discipline.
- Proven track record in delivering 1st time success with complex mixed signal IC’s.
- Experience of mixed signal simulation techniques and tools, including Spectre, AMS and Digital simulation.
- Knowledge of System-Verilog.
- Testbench design with verification frameworks like UVM/OVM, e, VMM.
- Modelling of Analog subsystems using System Verilog and VerilogA/AMS.
- Experience of analog and digital design.
- Object orientated programming (OOP) - Use of OOP design patterns.
- Scripting experience with Python, Ruby, sh/csh, TCL, Make, Perl.
- Strong ability to interpret results and resolve problems.
- Highly developed communication skills.
- An innovative, creative, lateral thinking problem solver.